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Using a bigger (or bolder) font than usual is called shouting and it's quite noisy.
If the Lord God Almighty had consulted me before embarking upon the Creation, I would have recommended something simpler.
-- Alfonso the Wise, 13th Century King of Castile.
This is going on my arrogant assumptions. You may have a superb reason why I'm completely wrong.
-- Iain Clarke
[My articles]
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Um,okay, here is the reason:
Cos I'm knew here, and I haven't got used to the rules here...
So, sorry for bothering. All I want is a little piece of advice.
TKS, though.
best,
Blade
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CPallini wrote: Shouting will not help you.
Unless you're drowning into the sea.
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Actually I'm drowning in a ocean of bytes, right now.
The (in)famous thread hijacker.
If the Lord God Almighty had consulted me before embarking upon the Creation, I would have recommended something simpler.
-- Alfonso the Wise, 13th Century King of Castile.
This is going on my arrogant assumptions. You may have a superb reason why I'm completely wrong.
-- Iain Clarke
[My articles]
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Hello everyone,
Two questions after readnig this article,
http://www.microsoft.com/msj/0298/hood0298.aspx
1.
why using LEA to do multiplication is faster than using MUL?
"Using "LEA EAX,[EAX*4+EAX]" turns out to be faster than the MUL instruction."
2.
"The TEB's linear address can be found at offset 0x18 in the TEB." -- what means linear address? Something like array, which elements are put next to each other? What means non-linear address?
thanks in advance,
George
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George_George wrote: why using LEA to do multiplication is faster than using MUL?
"Using "LEA EAX,[EAX*4+EAX]" turns out to be faster than the MUL instruction."
lea seems to be an addressing instruction, which means it probably must execute in a single cycle and therefore would surely be faster than mul. On the other side, because it is an addressing instruction, think if you will be able to multiply very large numbers this way. There must be surely limitations on that. mul can work with large numbers also.
Thanks for the question, the search for an answer got me an interesting read.
Link: Wikibooks->Reverse Engineering->CodeTransformations->Common instruction substitutions[^]
Warning: I'm not a full time assembly programmer and I may not be accurate.
My assumptions: An X86 Processor, pentium class.
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Thanks Rajesh!
1.
"it probably must execute in a single cycle and therefore would surely be faster than mul" -- do you have any documents to support this statement? Where to look for documents for cycles needed for a specific instruction (e.g. LEA and MUL)?
2.
Any ideas to my question #2?
regards,
George
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George_George wrote: "it probably must execute in a single cycle and therefore would surely be faster than mul" -- do you have any documents to support this statement?
With the LEA instruction, the x86 processor can now perform a 3-number add, with something like a C expression "a = b + c + 10;" translating into EAX = EBX+ECX+10 and being coded into one instruction:
LEA EAX,[EBX+ECX+10]
Notice that no memory is actually referenced. LEA is used merely to calculate values by performing the addition of a base register (EBX) with an index register (ECX) with some constant displacement (10). This is what the address generation unit (AGU) does, allowing the processor to quickly calculate addresses of array elements, screen pixel locations, and do some basic arithmetic in one clock cycle. Source: http://www.emulators.com/docs/pentium_1.htm[^]
Refer to pages 6 & 7 in this PDF (Pentium: Not the same old song)[^]. This too supports my earlier statement.
Also, read "Handy info on speeding up integer instructions" in this page[^]
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Thanks Rajesh,
My question item 1 is answered. Any ideas to my question item 2? About what mean linear and non-linear address?
regards,
George
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I'll be happy to hear your feedback on "why" you voted the post down. Correct me if I said something wrong there, please.
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What means vote post down? I vote for 5 because I like your answer. You want 6?
regards,
George
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Nope, I knew it wouldn't be you. Someone has marked it as an unhelpful answer and I wanted their feedback in particular, so that I can know if I my answer was wrong or how can I make it any better.
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Take it easy, man!
Rajesh, just enjoy discussion with people around the world which have different options for the same question.
regards,
George
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The point was that there was nothing wrong in my answer (my opinion) and someone still voted it down. I just wanted their feedback in particular to know if anything was wrong with my answer, so that I can know something new. Not that I care for the vote.
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whoso ever downvoted you .. will be beaten with stick! any ways le me also square it of!
"Opinions are neither right nor wrong. I cannot change your opinion. I can, however, change what influences your opinion." - David Crow
Never mind - my own stupidity is the source of every "problem" - Mixture
cheers,
Alok Gupta
VC Forum Q&A :- I/ IV
Support CRY- Child Relief and You/xml>
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Thanks man. You're kind. 
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George_George wrote: why using LEA to do multiplication is faster than using MUL?
You'd have to know about the internal architecture and circuitry of the CPU to answer that; I don't and I doubt there would be many people except for people that work (or have worked) at Intel that would.
George_George wrote: "The TEB's linear address can be found at offset 0x18 in the TEB." -- what means linear address? Something like array, which elements are put next to each other? What means non-linear address?
To understand what's going on here you have to know a little about Intel CPUs and segment registers. Basically C/C++ has no concept of segment registers and such (it assumes a linear address space) so this is a page-table mapping trick done by the OS to make the TEB addressable in such an environment.
Steve
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Thanks Steve,
1.
Where to look for documents for cycles needed for a specific instruction (e.g. LEA and MUL)?
2.
"it assumes a linear address space" -- it you mean low layer CPU/register or high layer C/C++?
regards,
George
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George_George wrote: Where to look for documents for cycles needed for a specific instruction (e.g. LEA and MUL)?
Download the datasheet for the CPU.
George_George wrote: "it assumes a linear address space" -- it you mean low layer CPU/register or high layer C/C++?
It's complicated and very low level. I suggest you start reading something like this[^].
Steve
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Thanks Steve,
"datasheet for the CPU" -- could you give me some links or keywords to search? I am new to this topic.
regards,
George
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Have you Googled for "Pentium Datasheet"?
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Thanks Steve,
1.
I have read the link you referred. It talks about how protected mode is using segment based accessment model. But during the whole article, it never mentioned what means linear and non-lnear -- and this is my question.
2.
Could you provide a link for the data sheet you means please? Sorry I am new to this area.
regards,
George
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George_George wrote: I have read the link you referred. It talks about how protected mode is using segment based accessment model. But during the whole article, it never mentioned what means linear and non-lnear -- and this is my question.
This is an oversimplification, but here goes.
In protected mode a number of segment register are used:
CS : Code segment
DS : Data segment
SS : Stack segment
ES : Extra segment
FS : Another extra segment
GS : Yet another extra segment
Different instructions use different segments for different purposes (some instructions also allow for the default segment used to be overridden). Each segment can represent a physically distinct linearly addressable memory space; it’s possible to set things up so that memory addressable in one segment is not addressable in another. In Windows most of the segment registers map to the same memory, which is good as languages such as C/C++ have no concept of segments (or you could think of it as only supporting one segment). The FS segment is an exception however and serves a special purpose: the memory in it is the TIB. So languages like C/C++ can access the TIB the same memory is also mapped into the other segments. The address in the other segments where it’s mapped is stored at FS:[0x18].
George_George wrote: Could you provide a link for the data sheet you means please? Sorry I am new to this area.
See here[^]. Makes good bedtime reading¿
Steve
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Thanks Steve,
1.
I understand the concept of segment. My question is what means linear and non-linear address? My confusion is, I did some search, but can not find any concept like linear or non-linear. Any comments or ideas?
2.
Sorry I am new to Intel manual, and looks like there is quite a few. To look up instruction machine cycle for x64, I should look at the following two manuals?
Intel® 64 and IA-32 Architectures Software Developer's Manual
Volume 2A: Instruction Set Reference, A-M
Describes the format of the instruction and provides reference pages for instructions (from A to M). This volume also contains the table of contents for both Volumes 2A and 2B.
Download ›
(PDF 2.99MB) Order a printed copy ›
(SKU #253666)
Intel® 64 and IA-32 Architectures Software Developer's Manual
Volume 2B: Instruction Set Reference, N-Z
Provides reference pages for instructions (from N to Z). VMX instructions are treated in a separate chapter. This volume also contains the appendices and index support for Volumes 2A and 2B.
Download ›
(PDF 5.60MB) Order a printed copy ›
(SKU #253667)
regards,
George
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