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AnswerRe: cant trigger relay with LPT port Pin
Trollslayer30-Nov-06 9:18
mentorTrollslayer30-Nov-06 9:18 
GeneralRe: cant trigger relay with LPT port Pin
Muammar©2-Dec-06 19:22
Muammar©2-Dec-06 19:22 
QuestionAdapter for PCI-x to PCIe ?? Pin
pavanbabut3-Nov-06 7:20
pavanbabut3-Nov-06 7:20 
AnswerRe: Adapter for PCI-x to PCIe ?? Pin
Dan Neely3-Nov-06 8:13
Dan Neely3-Nov-06 8:13 
QuestionGarmin GPS 18 Pin
Eng. Noora1-Nov-06 8:29
Eng. Noora1-Nov-06 8:29 
AnswerRe: Garmin GPS 18 Pin
markkuk4-Nov-06 1:58
markkuk4-Nov-06 1:58 
QuestionPCI Express and Memory mapped I/O! Pin
adrianuswiedewanus1-Nov-06 4:20
adrianuswiedewanus1-Nov-06 4:20 
AnswerRe: PCI Express and Memory mapped I/O! Pin
Mike Dimmick1-Nov-06 6:22
Mike Dimmick1-Nov-06 6:22 
DMA is the ability for the device to take control of the system's memory bus (become the 'bus master') and write directly to system memory locations without the need for software running on the system's host processor.

This is really a logical 'bus' concept dating from the time when everything was directly connected to the (single) processor's address and data bus pins. Normally the processor was 'bus master' - it emitted the necessary voltages to drive the address and data buses. For another device to write to or read from the system memory (or any other device connected to the memory buses), a Direct Memory Access [DMA], it had to ask the processor to put its bus drivers into high-impedance mode, so that it was not interfering, electrically, with the buses. When finished, the device then relinquishes its master status.

On a modern system there are many, many different buses which run at different speeds and have different electrical characteristics. To cross between these different buses, there are different bus controllers. On Intel processor-based systems, the key one for PCI Express operations is the Memory Controller Hub, which connects the processors' Front Side Bus to the memory buses (now normally two), the PCI Express channels, and the Inter-Hub Transport which connects to the I/O Controller Hub (on Intel chipsets). On AMD processor-based systems, the memory buses connect directly to the processor, while the PCI Express channels are connected to a PCI Express controller which connects to the processor(s) over a HyperTransport link.

Any operations that involve reading from or writing to a PCI Express device will need a PCI Express read or write sequence, whether driven by the processor or by the device itself. The PCI Express transaction is the read or write operation.

To get the results of a DMA write operation (i.e. the device writes to memory), you simply need to read from the physical memory addresses that the DMA operation wrote to. Conversely, to control a DMA read operation, you need to write the data to be transferred to a particular physical memory location (or locations), and program the device to perform the DMA from those locations. Actually, you can normally program the device to transfer the data from locations that already contain the correct data.

Stability. What an interesting concept. -- Chris Maunder

QuestionNEC MAC Address Pin
Reader Man San31-Oct-06 18:52
professionalReader Man San31-Oct-06 18:52 
AnswerRe: NEC MAC Address Pin
S Douglas31-Oct-06 19:44
professionalS Douglas31-Oct-06 19:44 
GeneralRe: NEC MAC Address Pin
Reader Man San31-Oct-06 20:53
professionalReader Man San31-Oct-06 20:53 
GeneralRe: NEC MAC Address Pin
S Douglas31-Oct-06 21:36
professionalS Douglas31-Oct-06 21:36 
GeneralRe: NEC MAC Address Pin
Reader Man San1-Nov-06 1:33
professionalReader Man San1-Nov-06 1:33 
AnswerRe: NEC MAC Address Pin
fat_boy2-Nov-06 1:47
fat_boy2-Nov-06 1:47 
GeneralRe: NEC MAC Address Pin
Reader Man San3-Nov-06 18:39
professionalReader Man San3-Nov-06 18:39 
GeneralRe: NEC MAC Address Pin
fat_boy5-Nov-06 22:06
fat_boy5-Nov-06 22:06 
QuestionSpontaneous pseudo-random system beeps Pin
Paul Vickery30-Oct-06 6:00
professionalPaul Vickery30-Oct-06 6:00 
AnswerRe: Spontaneous pseudo-random system beeps Pin
Dave Kreskowiak30-Oct-06 7:12
mveDave Kreskowiak30-Oct-06 7:12 
GeneralRe: Spontaneous pseudo-random system beeps Pin
Paul Vickery31-Oct-06 3:46
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GeneralRe: Spontaneous pseudo-random system beeps Pin
Dave Kreskowiak31-Oct-06 6:47
mveDave Kreskowiak31-Oct-06 6:47 
GeneralRe: Spontaneous pseudo-random system beeps Pin
Paul Vickery9-Nov-06 2:37
professionalPaul Vickery9-Nov-06 2:37 
AnswerRe: Spontaneous pseudo-random system beeps Pin
S Douglas31-Oct-06 19:48
professionalS Douglas31-Oct-06 19:48 
QuestionPlease help me Pin
Boshkash30-Oct-06 5:16
Boshkash30-Oct-06 5:16 
AnswerRe: Please help me Pin
Dan Neely30-Oct-06 5:50
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GeneralRe: Please help me Pin
Boshkash30-Oct-06 6:36
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