Cortex M3 - testing an internal interrupt

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C

testing

ARM

assembler

Hello,
I have a Cortex M3 based SOC and I need to test the response to a RAM ECC error. To do that I would need to simulate the interrupt in some way, problem is it is an internal interrupt, so no pins to drive manually, and apparently there is no way to force it to happen - I can't force a parity error externally and the registers that manage the interrupt are not writable by software (with the exception of the request to clear it fo course).

Does anyone know some kind of magic to test it? I repeat for clarity: I need a way to force the microcontroller to react to an error on the RAM ECC at my request.

Thank you all,
Denis

What I have tried:

Surfing through a lot of poor documentation on the actual SOC, will try delving deep into ARM Assembler next checking opcodes one by one.